cpldfit:  version K.39                              Xilinx Inc.
                                  Fitter Report
Design Name: main                                Date:  4- 5-2009,  5:32PM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
45 /72  ( 62%) 113 /360  ( 31%) 67 /216 ( 31%)   25 /72  ( 35%) 9  /34  ( 26%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          17/18       18/54       43/90       4/ 9
FB2           6/18       19/54       23/90       1/ 9
FB3          15/18       19/54       35/90       4/ 9
FB4           7/18       11/54       12/90       0/ 7
             -----       -----       -----      -----    
             45/72       67/216     113/360      9/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK_FAST' mapped onto global clock net GCK1.
Signal 'CLK_SLOW' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :     7      28
Output        :    6           6    |  GCK/IO           :     2       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    2           2    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      9           9

** Power Data **

There are 45 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 6 Outputs **

Signal                                                                                                               Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                                                                                                 Pts   Inps          No.  Type    Use     Mode Rate State
LED<0>                                                                                                               2     3     FB1_2   1~   I/O     O       STD  SLOW RESET
LED<1>                                                                                                               3     6     FB1_5   2~   I/O     O       STD  SLOW SET
AUDIO<0>                                                                                                             3     3     FB3_11  18~  I/O     O       STD  FAST 
AUDIO<1>                                                                                                             3     5     FB3_15  20~  I/O     O       STD  FAST RESET
AUDIO<3>                                                                                                             3     6     FB3_16  24~  I/O     O       STD  FAST RESET
AUDIO<2>                                                                                                             3     3     FB3_17  22~  I/O     O       STD  FAST 

** 39 Buried Nodes **

Signal                                                                                                               Total Total Loc     Pwr  Reg Init
Name                                                                                                                 Pts   Inps          Mode State
song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2                                                   1     2     FB1_3   STD  
song_ind_or0000/song_ind_or0000_D2                                                                                   2     7     FB1_4   STD  
song_ind<5>                                                                                                          2     8     FB1_6   STD  RESET
song_ind<4>                                                                                                          2     7     FB1_7   STD  RESET
song_ind<3>                                                                                                          2     5     FB1_8   STD  RESET
song_ind<2>                                                                                                          2     4     FB1_9   STD  RESET
song_ind<1>                                                                                                          2     4     FB1_10  STD  RESET
sine_tbl_ind_Maddsub__addsub0000_Mxor_Result<1>__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result<1>__xor0000_D  2     2     FB1_11  STD  
sine_tbl_ind<0>                                                                                                      2     3     FB1_12  STD  RESET
$OpTx$FX_DC$116                                                                                                      2     6     FB1_13  STD  
note<2>/note<2>_D2                                                                                                   3     6     FB1_14  STD  
note<0>/note<0>_D2                                                                                                   3     6     FB1_15  STD  
N35/N35_D2                                                                                                           4     6     FB1_16  STD  
Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2                                                                         4     5     FB1_17  STD  
note<1>/note<1>_D2                                                                                                   5     6     FB1_18  STD  
song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2                                               1     4     FB2_2   STD  
$OpTx$FX_DC$111                                                                                                      1     3     FB2_14  STD  
song_delay<5>                                                                                                        2     6     FB2_15  STD  RESET
song_delay<4>                                                                                                        2     4     FB2_16  STD  RESET
song_delay<3>                                                                                                        2     3     FB2_17  STD  RESET
N0/N0_D2                                                                                                             15    13    FB2_18  STD  
sine_cnt_en                                                                                                          1     8     FB3_4   STD  RESET
rst                                                                                                                  1     1     FB3_5   STD  SET
Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2                                                 1     4     FB3_6   STD  
Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2                                                 1     2     FB3_7   STD  
$OpTx$FX_DC$127                                                                                                      1     5     FB3_8   STD  
note_cnt<0>                                                                                                          2     4     FB3_9   STD  RESET
note_cnt<5>                                                                                                          3     5     FB3_10  STD  RESET
note_cnt<4>                                                                                                          3     8     FB3_12  STD  RESET
note_cnt<2>                                                                                                          3     5     FB3_13  STD  RESET
note_cnt<1>                                                                                                          3     5     FB3_14  STD  RESET
note_cnt<3>                                                                                                          4     6     FB3_18  STD  RESET
song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2                                               1     3     FB4_12  STD  
song_delay<0>                                                                                                        1     2     FB4_13  STD  RESET
song_ind_0__or0000/song_ind_0__or0000_D2                                                                             2     8     FB4_14  STD  
song_delay_or0000/song_delay_or0000_D2                                                                               2     8     FB4_15  STD  
song_delay<6>                                                                                                        2     3     FB4_16  STD  RESET
song_delay<2>                                                                                                        2     5     FB4_17  STD  RESET
song_delay<1>                                                                                                        2     3     FB4_18  STD  RESET

** 3 Inputs **

Signal                                                                                                               Loc     Pin  Pin     Pin     
Name                                                                                                                         No.  Type    Use     
CLK_FAST                                                                                                             FB1_9   5~   GCK/I/O GCK
CLK_SLOW                                                                                                             FB1_11  6~   GCK/I/O GCK
TASTER_RES                                                                                                           FB2_8   38~  I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               18/36
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
LED<0>                2       0     0   3     FB1_2   1~    I/O     O
song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2
                      1       0     0   4     FB1_3         (b)     (b)
song_ind_or0000/song_ind_or0000_D2
                      2       0     0   3     FB1_4         (b)     (b)
LED<1>                3       0     0   2     FB1_5   2~    I/O     O
song_ind<5>           2       0     0   3     FB1_6   3     I/O     (b)
song_ind<4>           2       0     0   3     FB1_7         (b)     (b)
song_ind<3>           2       0     0   3     FB1_8   4     I/O     (b)
song_ind<2>           2       0     0   3     FB1_9   5     GCK/I/O GCK
song_ind<1>           2       0     0   3     FB1_10        (b)     (b)
sine_tbl_ind_Maddsub__addsub0000_Mxor_Result<1>__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result<1>__xor0000_D
                      2       0     0   3     FB1_11  6     GCK/I/O GCK
sine_tbl_ind<0>       2       0     0   3     FB1_12        (b)     (b)
$OpTx$FX_DC$116       2       0     0   3     FB1_13        (b)     (b)
note<2>/note<2>_D2    3       0     0   2     FB1_14  7     GCK/I/O (b)
note<0>/note<0>_D2    3       0     0   2     FB1_15  8     I/O     (b)
N35/N35_D2            4       0     0   1     FB1_16        (b)     (b)
Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2
                      4       0     0   1     FB1_17  9     I/O     (b)
note<1>/note<1>_D2    5       0     0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$116                                7: N35/N35_D2        13: song_ind<3> 
  2: AUDIO<1>                                       8: rst               14: song_ind<4> 
  3: AUDIO<3>                                       9: sine_cnt_en       15: song_ind<5> 
  4: LED<0>                                        10: sine_tbl_ind<0>   16: song_ind_0__or0000/song_ind_0__or0000_D2 
  5: LED<1>                                        11: song_ind<1>       17: song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2 
  6: Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2  12: song_ind<2>       18: song_ind_or0000/song_ind_or0000_D2 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
LED<0>               ...X...X.......X........................ 3
song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2 
                     ...X......X............................. 2
song_ind_or0000/song_ind_or0000_D2 
                     .......X...XXXXXX....................... 7
LED<1>               .XX.X..XXX.............................. 6
song_ind<5>          X..........XXXXXXX...................... 8
song_ind<4>          X..........XXX.XXX...................... 7
song_ind<3>          ...........XX..XXX...................... 5
song_ind<2>          ...........X...XXX...................... 4
song_ind<1>          ...X......X....X.X...................... 4
sine_tbl_ind_Maddsub__addsub0000_Mxor_Result<1>__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result<1>__xor0000_D 
                     .X..X................................... 2
sine_tbl_ind<0>      .......XXX.............................. 3
$OpTx$FX_DC$116      ...........XXX.XXX...................... 6
note<2>/note<2>_D2   .....X.....XXXX.X....................... 6
note<0>/note<0>_D2   ...X.XX....XXX.......................... 6
N35/N35_D2           .....X....XXXXX......................... 6
Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2 
                     ..........XXXXX......................... 5
note<1>/note<1>_D2   ...X......XXXXX......................... 6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               19/35
Number of signals used by logic mapping into function block:  19
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB2_1         (b)     (b)
song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2
                      1       0     0   4     FB2_2   35    I/O     (b)
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   36    I/O     
(unused)              0       0     0   5     FB2_6   37    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   38    I/O     I
(unused)              0       0     0   5     FB2_9   39    GSR/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  40    GTS/I/O 
(unused)              0       0     0   5     FB2_12        (b)     
(unused)              0       0     0   5     FB2_13        (b)     
$OpTx$FX_DC$111       1       0     0   4     FB2_14  42    GTS/I/O (b)
song_delay<5>         2       0     0   3     FB2_15  43    I/O     (b)
song_delay<4>         2       0   \/2   1     FB2_16        (b)     (b)
song_delay<3>         2       2<- \/5   0     FB2_17  44    I/O     (b)
N0/N0_D2             15      10<-   0   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$127                                                        8: note_cnt<2>       14: song_delay<5> 
  2: Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2   9: note_cnt<3>       15: song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2 
  3: note<0>/note<0>_D2                                                    10: note_cnt<4>       16: song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2 
  4: note<1>/note<1>_D2                                                    11: note_cnt<5>       17: song_delay_or0000/song_delay_or0000_D2 
  5: note<2>/note<2>_D2                                                    12: song_delay<3>     18: song_ind<3> 
  6: note_cnt<0>                                                           13: song_delay<4>     19: song_ind<4> 
  7: note_cnt<1>                                                          

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2 
                     ...........XXXX......................... 4
$OpTx$FX_DC$111      ..XXX................................... 3
song_delay<5>        ...........XXXXXX....................... 6
song_delay<4>        ...........XX.X.X....................... 4
song_delay<3>        ...........X..X.X....................... 3
N0/N0_D2             XXXXXXXXXXX......XX..................... 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               19/35
Number of signals used by logic mapping into function block:  19
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   11    I/O     
(unused)              0       0     0   5     FB3_3         (b)     
sine_cnt_en           1       0     0   4     FB3_4         (b)     (b)
rst                   1       0     0   4     FB3_5   12    I/O     (b)
Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2
                      1       0     0   4     FB3_6         (b)     (b)
Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2
                      1       0     0   4     FB3_7         (b)     (b)
$OpTx$FX_DC$127       1       0     0   4     FB3_8   13    I/O     (b)
note_cnt<0>           2       0     0   3     FB3_9   14    I/O     (b)
note_cnt<5>           3       0     0   2     FB3_10        (b)     (b)
AUDIO<0>              3       0     0   2     FB3_11  18~   I/O     O
note_cnt<4>           3       0     0   2     FB3_12        (b)     (b)
note_cnt<2>           3       0     0   2     FB3_13        (b)     (b)
note_cnt<1>           3       0     0   2     FB3_14  19    I/O     (b)
AUDIO<1>              3       0     0   2     FB3_15  20~   I/O     O
AUDIO<3>              3       0     0   2     FB3_16  24~   I/O     O
AUDIO<2>              3       0     0   2     FB3_17  22~   I/O     O
note_cnt<3>           4       0     0   1     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$111                                                        8: N35/N35_D2        14: note_cnt<4> 
  2: AUDIO<1>                                                               9: TASTER_RES        15: note_cnt<5> 
  3: AUDIO<3>                                                              10: note_cnt<0>       16: rst 
  4: LED<1>                                                                11: note_cnt<1>       17: sine_cnt_en 
  5: Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2  12: note_cnt<2>       18: sine_tbl_ind<0> 
  6: Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2  13: note_cnt<3>       19: sine_tbl_ind_Maddsub__addsub0000_Mxor_Result<1>__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result<1>__xor0000_D 
  7: N0/N0_D2                                                             

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
sine_cnt_en          X........XXXXXXX........................ 8
rst                  ........X............................... 1
Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2 
                     ....X......XXX.......................... 4
Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2 
                     .........XX............................. 2
$OpTx$FX_DC$127      .........XXXXX.......................... 5
note_cnt<0>          ......XX.X.....X........................ 4
note_cnt<5>          .....XXX......XX........................ 5
AUDIO<0>             .XX..............X...................... 3
note_cnt<4>          ....XXXX...XXX.X........................ 8
note_cnt<2>          ....X.XX...X...X........................ 5
note_cnt<1>          ......XX.XX....X........................ 5
AUDIO<1>             .X.............XXXX..................... 5
AUDIO<3>             ..XX...........XXXX..................... 6
AUDIO<2>             .XX..............X...................... 3
note_cnt<3>          ....X.XX...XX..X........................ 6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               11/43
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   25    I/O     
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   26    I/O     
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   27    I/O     
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  28    I/O     
song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2
                      1       0     0   4     FB4_12        (b)     (b)
song_delay<0>         1       0     0   4     FB4_13        (b)     (b)
song_ind_0__or0000/song_ind_0__or0000_D2
                      2       0     0   3     FB4_14  29    I/O     (b)
song_delay_or0000/song_delay_or0000_D2
                      2       0     0   3     FB4_15  33    I/O     (b)
song_delay<6>         2       0     0   3     FB4_16        (b)     (b)
song_delay<2>         2       0     0   3     FB4_17  34    I/O     (b)
song_delay<1>         2       0     0   3     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: rst                5: song_delay<3>      9: song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2 
  2: song_delay<0>      6: song_delay<4>     10: song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2 
  3: song_delay<1>      7: song_delay<5>     11: song_delay_or0000/song_delay_or0000_D2 
  4: song_delay<2>      8: song_delay<6>    

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2 
                     .XXX.................................... 3
song_delay<0>        .X........X............................. 2
song_ind_0__or0000/song_ind_0__or0000_D2 
                     XXXXXXXX................................ 8
song_delay_or0000/song_delay_or0000_D2 
                     XXXXXXXX................................ 8
song_delay<6>        .......X.XX............................. 3
song_delay<2>        .XXX....X.X............................. 5
song_delay<1>        .XX.......X............................. 3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$FX_DC$111 <= (NOT note(1)/note(1)_D2 AND NOT note(0)/note(0)_D2 AND 
	note(2)/note(2)_D2);


$OpTx$FX_DC$116 <= ((song_ind_0__or0000/song_ind_0__or0000_D2 AND 
	song_ind_or0000/song_ind_or0000_D2)
	OR (song_ind(2) AND song_ind(3) AND song_ind(4) AND 
	song_ind_0__or0000/song_ind_0__or0000_D2 AND 
	song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));


$OpTx$FX_DC$127 <= (NOT note_cnt(2) AND note_cnt(1) AND NOT note_cnt(3) AND 
	NOT note_cnt(4) AND NOT note_cnt(0));


AUDIO(0) <= NOT (AUDIO(1)
	 XOR 
AUDIO(0) <= NOT (((AUDIO(3) AND sine_tbl_ind(0))
	OR (NOT AUDIO(3) AND NOT sine_tbl_ind(0))));

FDCPE_AUDIO1: FDCPE port map (AUDIO(1),AUDIO_D(1),CLK_FAST,'0','0');
AUDIO_D(1) <= ((AUDIO(1) AND NOT rst AND NOT sine_cnt_en)
	OR (sine_tbl_ind(0) AND NOT rst AND sine_cnt_en AND 
	NOT sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D)
	OR (NOT sine_tbl_ind(0) AND NOT rst AND sine_cnt_en AND 
	sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D));


AUDIO(2) <= ((AUDIO(1) AND AUDIO(3))
	OR (AUDIO(1) AND sine_tbl_ind(0))
	OR (AUDIO(3) AND sine_tbl_ind(0)));

FTCPE_AUDIO3: FTCPE port map (AUDIO(3),AUDIO_T(3),CLK_FAST,'0','0');
AUDIO_T(3) <= ((AUDIO(3) AND rst)
	OR (sine_tbl_ind(0) AND NOT rst AND sine_cnt_en AND NOT LED(1) AND 
	sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D)
	OR (NOT sine_tbl_ind(0) AND NOT rst AND sine_cnt_en AND LED(1) AND 
	sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D));



FDCPE_LED0: FDCPE port map (LED(0),LED_D(0),CLK_SLOW,'0','0');
LED_D(0) <= ((LED(0) AND NOT song_ind_0__or0000/song_ind_0__or0000_D2)
	OR (NOT LED(0) AND NOT rst AND 
	song_ind_0__or0000/song_ind_0__or0000_D2));

FTCPE_LED1: FTCPE port map (LED(1),LED_T(1),CLK_FAST,'0','0');
LED_T(1) <= ((rst AND LED(1))
	OR (NOT AUDIO(1) AND NOT AUDIO(3) AND sine_tbl_ind(0) AND 
	sine_cnt_en AND LED(1))
	OR (AUDIO(1) AND AUDIO(3) AND NOT sine_tbl_ind(0) AND NOT rst AND 
	sine_cnt_en AND NOT LED(1)));


Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2 <= (note_cnt(1) AND note_cnt(0));


Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2 <= (note_cnt(2) AND note_cnt(3) AND note_cnt(4) AND 
	Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2);


Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2 <= ((song_ind(2) AND NOT song_ind(3) AND NOT song_ind(4) AND 
	NOT song_ind(5))
	OR (song_ind(2) AND NOT song_ind(3) AND NOT song_ind(5) AND 
	NOT song_ind(1))
	OR (song_ind(2) AND NOT song_ind(4) AND NOT song_ind(5) AND 
	NOT song_ind(1))
	OR (NOT song_ind(2) AND NOT song_ind(3) AND NOT song_ind(4) AND 
	song_ind(5)));


N0/N0_D2 <= ((EXP6_.EXP)
	OR (song_delay(3).EXP)
	OR (NOT note_cnt(5) AND NOT note_cnt(4) AND note(0)/note(0)_D2)
	OR (NOT note_cnt(5) AND NOT note_cnt(4) AND NOT note(2)/note(2)_D2)
	OR (NOT note_cnt(5) AND NOT note_cnt(3) AND note(0)/note(0)_D2 AND 
	note(2)/note(2)_D2)
	OR (NOT note(1)/note(1)_D2 AND note(0)/note(0)_D2 AND 
	note(2)/note(2)_D2 AND NOT $OpTx$FX_DC$127)
	OR (NOT song_ind(3) AND NOT song_ind(4) AND NOT note_cnt(5) AND 
	NOT note_cnt(4) AND note(1)/note(1)_D2));


N35/N35_D2 <= ((song_ind(3) AND song_ind(5))
	OR (NOT song_ind(2) AND song_ind(5) AND 
	NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
	OR (song_ind(2) AND NOT song_ind(3) AND song_ind(4) AND 
	NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
	OR (song_ind(2) AND NOT song_ind(4) AND song_ind(1) AND 
	NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2));


note(0)/note(0)_D2 <= ((Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
	OR (song_ind(2) AND NOT N35/N35_D2)
	OR (NOT LED(0) AND NOT song_ind(3) AND NOT song_ind(4) AND NOT N35/N35_D2));


note(1)/note(1)_D2 <= ((song_ind(2) AND song_ind(3) AND song_ind(4) AND 
	NOT song_ind(5))
	OR (NOT song_ind(2) AND song_ind(3) AND NOT song_ind(4) AND 
	NOT song_ind(5))
	OR (NOT song_ind(2) AND NOT song_ind(3) AND song_ind(4) AND 
	NOT song_ind(5))
	OR (LED(0) AND NOT song_ind(2) AND NOT song_ind(4) AND 
	NOT song_ind(5) AND NOT song_ind(1))
	OR (NOT LED(0) AND NOT song_ind(2) AND NOT song_ind(4) AND 
	NOT song_ind(5) AND song_ind(1)));


note(2)/note(2)_D2 <= ((song_ind(2) AND 
	NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
	OR (song_ind(5) AND 
	NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
	OR (NOT song_ind(3) AND NOT song_ind(4) AND 
	NOT song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2 AND NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2));

FDCPE_note_cnt0: FDCPE port map (note_cnt(0),note_cnt_D(0),CLK_FAST,'0','0');
note_cnt_D(0) <= ((NOT rst AND note_cnt(0) AND N35/N35_D2)
	OR (NOT rst AND NOT note_cnt(0) AND N0/N0_D2));

FDCPE_note_cnt1: FDCPE port map (note_cnt(1),note_cnt_D(1),CLK_FAST,'0','0');
note_cnt_D(1) <= ((NOT rst AND note_cnt(1) AND N35/N35_D2)
	OR (NOT rst AND note_cnt(1) AND NOT note_cnt(0) AND N0/N0_D2)
	OR (NOT rst AND NOT note_cnt(1) AND note_cnt(0) AND N0/N0_D2));

FDCPE_note_cnt2: FDCPE port map (note_cnt(2),note_cnt_D(2),CLK_FAST,'0','0');
note_cnt_D(2) <= ((NOT rst AND note_cnt(2) AND N35/N35_D2)
	OR (NOT rst AND note_cnt(2) AND N0/N0_D2 AND 
	NOT Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2)
	OR (NOT rst AND NOT note_cnt(2) AND N0/N0_D2 AND 
	Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2));

FDCPE_note_cnt3: FDCPE port map (note_cnt(3),note_cnt_D(3),CLK_FAST,'0','0');
note_cnt_D(3) <= ((NOT rst AND note_cnt(3) AND N35/N35_D2)
	OR (NOT rst AND NOT note_cnt(2) AND note_cnt(3) AND N0/N0_D2)
	OR (NOT rst AND note_cnt(3) AND N0/N0_D2 AND 
	NOT Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2)
	OR (NOT rst AND note_cnt(2) AND NOT note_cnt(3) AND N0/N0_D2 AND 
	Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2));

FDCPE_note_cnt4: FDCPE port map (note_cnt(4),note_cnt_D(4),CLK_FAST,'0','0');
note_cnt_D(4) <= ((NOT rst AND note_cnt(4) AND N35/N35_D2)
	OR (NOT rst AND note_cnt(4) AND N0/N0_D2 AND 
	NOT Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2)
	OR (NOT rst AND note_cnt(2) AND note_cnt(3) AND NOT note_cnt(4) AND 
	N0/N0_D2 AND 
	Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2));

FDCPE_note_cnt5: FDCPE port map (note_cnt(5),note_cnt_D(5),CLK_FAST,'0','0');
note_cnt_D(5) <= ((NOT rst AND note_cnt(5) AND N35/N35_D2)
	OR (NOT rst AND note_cnt(5) AND N0/N0_D2 AND 
	NOT Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2)
	OR (NOT rst AND NOT note_cnt(5) AND N0/N0_D2 AND 
	Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2));

FDCPE_rst: FDCPE port map (rst,NOT TASTER_RES,CLK_FAST,'0','0');

FDCPE_sine_cnt_en: FDCPE port map (sine_cnt_en,sine_cnt_en_D,CLK_FAST,'0','0');
sine_cnt_en_D <= (NOT rst AND NOT note_cnt(2) AND NOT note_cnt(5) AND NOT note_cnt(1) AND 
	NOT note_cnt(3) AND NOT note_cnt(4) AND NOT note_cnt(0) AND NOT $OpTx$FX_DC$111);

FDCPE_sine_tbl_ind0: FDCPE port map (sine_tbl_ind(0),sine_tbl_ind_D(0),CLK_FAST,'0','0');
sine_tbl_ind_D(0) <= ((sine_tbl_ind(0) AND NOT rst AND NOT sine_cnt_en)
	OR (NOT sine_tbl_ind(0) AND NOT rst AND sine_cnt_en));


sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D <= LED(1)
	 XOR 
sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D <= AUDIO(1);

FDCPE_song_delay0: FDCPE port map (song_delay(0),song_delay_D(0),CLK_SLOW,'0','0');
song_delay_D(0) <= (NOT song_delay(0) AND 
	NOT song_delay_or0000/song_delay_or0000_D2);

FDCPE_song_delay1: FDCPE port map (song_delay(1),song_delay_D(1),CLK_SLOW,'0','0');
song_delay_D(1) <= ((song_delay(0) AND NOT song_delay(1) AND 
	NOT song_delay_or0000/song_delay_or0000_D2)
	OR (NOT song_delay(0) AND song_delay(1) AND 
	NOT song_delay_or0000/song_delay_or0000_D2));

FDCPE_song_delay2: FDCPE port map (song_delay(2),song_delay_D(2),CLK_SLOW,'0','0');
song_delay_D(2) <= ((song_delay(2) AND 
	NOT song_delay_or0000/song_delay_or0000_D2 AND 
	NOT song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2)
	OR (song_delay(0) AND song_delay(1) AND 
	NOT song_delay_or0000/song_delay_or0000_D2 AND 
	NOT song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2));

FDCPE_song_delay3: FDCPE port map (song_delay(3),song_delay(4).EXP,CLK_SLOW,'0','0');

FTCPE_song_delay4: FTCPE port map (song_delay(4),song_delay_T(4),CLK_SLOW,'0','0');
song_delay_T(4) <= ((song_delay(4) AND 
	song_delay_or0000/song_delay_or0000_D2)
	OR (song_delay(3) AND 
	NOT song_delay_or0000/song_delay_or0000_D2 AND 
	song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2));

FDCPE_song_delay5: FDCPE port map (song_delay(5),song_delay_D(5),CLK_SLOW,'0','0');
song_delay_D(5) <= ((song_delay(5) AND 
	NOT song_delay_or0000/song_delay_or0000_D2 AND 
	NOT song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2)
	OR (song_delay(3) AND song_delay(4) AND 
	NOT song_delay_or0000/song_delay_or0000_D2 AND 
	song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2 AND 
	NOT song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2));

FDCPE_song_delay6: FDCPE port map (song_delay(6),song_delay_D(6),CLK_SLOW,'0','0');
song_delay_D(6) <= ((song_delay(6) AND 
	NOT song_delay_or0000/song_delay_or0000_D2 AND 
	NOT song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2)
	OR (NOT song_delay(6) AND 
	NOT song_delay_or0000/song_delay_or0000_D2 AND 
	song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2));


song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2 <= (song_delay(0) AND song_delay(1) AND song_delay(2));


song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2 <= (song_delay(3) AND song_delay(4) AND song_delay(5) AND 
	song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2);


song_delay_or0000/song_delay_or0000_D2 <= ((rst)
	OR (NOT song_delay(0) AND song_delay(1) AND song_delay(2) AND 
	song_delay(3) AND NOT song_delay(4) AND song_delay(5) AND song_delay(6)));

FTCPE_song_ind1: FTCPE port map (song_ind(1),song_ind_T(1),CLK_SLOW,'0','0');
song_ind_T(1) <= ((LED(0) AND song_ind_0__or0000/song_ind_0__or0000_D2 AND 
	NOT song_ind_or0000/song_ind_or0000_D2)
	OR (song_ind(1) AND 
	song_ind_0__or0000/song_ind_0__or0000_D2 AND song_ind_or0000/song_ind_or0000_D2));

FTCPE_song_ind2: FTCPE port map (song_ind(2),song_ind_T(2),CLK_SLOW,'0','0');
song_ind_T(2) <= ((song_ind(2) AND 
	song_ind_0__or0000/song_ind_0__or0000_D2 AND song_ind_or0000/song_ind_or0000_D2)
	OR (song_ind_0__or0000/song_ind_0__or0000_D2 AND 
	NOT song_ind_or0000/song_ind_or0000_D2 AND 
	song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));

FTCPE_song_ind3: FTCPE port map (song_ind(3),song_ind_T(3),CLK_SLOW,'0','0');
song_ind_T(3) <= ((song_ind(3) AND 
	song_ind_0__or0000/song_ind_0__or0000_D2 AND song_ind_or0000/song_ind_or0000_D2)
	OR (song_ind(2) AND 
	song_ind_0__or0000/song_ind_0__or0000_D2 AND NOT song_ind_or0000/song_ind_or0000_D2 AND 
	song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));

FDCPE_song_ind4: FDCPE port map (song_ind(4),song_ind_D(4),CLK_SLOW,'0','0');
song_ind_D(4) <= ((song_ind(4) AND NOT $OpTx$FX_DC$116)
	OR (song_ind(2) AND song_ind(3) AND NOT song_ind(4) AND 
	song_ind_0__or0000/song_ind_0__or0000_D2 AND NOT song_ind_or0000/song_ind_or0000_D2 AND 
	song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));

FDCPE_song_ind5: FDCPE port map (song_ind(5),song_ind_D(5),CLK_SLOW,'0','0');
song_ind_D(5) <= ((song_ind(5) AND NOT $OpTx$FX_DC$116)
	OR (song_ind(2) AND song_ind(3) AND song_ind(4) AND 
	NOT song_ind(5) AND song_ind_0__or0000/song_ind_0__or0000_D2 AND 
	NOT song_ind_or0000/song_ind_or0000_D2 AND 
	song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));


song_ind_0__or0000/song_ind_0__or0000_D2 <= ((rst)
	OR (NOT song_delay(0) AND NOT song_delay(1) AND NOT song_delay(2) AND 
	NOT song_delay(3) AND NOT song_delay(4) AND NOT song_delay(5) AND NOT song_delay(6)));


song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2 <= (LED(0) AND song_ind(1));


song_ind_or0000/song_ind_or0000_D2 <= ((rst)
	OR (song_ind(2) AND NOT song_ind(3) AND NOT song_ind(4) AND 
	song_ind(5) AND song_ind_0__or0000/song_ind_0__or0000_D2 AND 
	song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XC9572XL-10-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 LED<0>                           23 GND                           
  2 LED<1>                           24 AUDIO<3>                      
  3 PGND                             25 PGND                          
  4 PGND                             26 PGND                          
  5 CLK_FAST                         27 PGND                          
  6 CLK_SLOW                         28 PGND                          
  7 PGND                             29 PGND                          
  8 PGND                             30 TDO                           
  9 PGND                             31 GND                           
 10 GND                              32 VCC                           
 11 PGND                             33 PGND                          
 12 PGND                             34 PGND                          
 13 PGND                             35 PGND                          
 14 PGND                             36 PGND                          
 15 TDI                              37 PGND                          
 16 TMS                              38 TASTER_RES                    
 17 TCK                              39 PGND                          
 18 AUDIO<0>                         40 PGND                          
 19 PGND                             41 VCC                           
 20 AUDIO<1>                         42 PGND                          
 21 VCC                              43 PGND                          
 22 AUDIO<2>                         44 PGND                          


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-PC44
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : ON
Set I/O Pin Termination                     : FLOAT
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 53
Pterm Limit                                 : 88