Timing Report

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Design Name main
Device, Speed (SpeedFile Version) XC9572XL, -10 (3.0)
Date Created Wed Apr 29 16:34:54 2009
Created By Timing Report Generator: version K.39
Copyright Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 10.000 ns.
Max. Clock Frequency (fSYSTEM) 100.000 MHz.
Limited by Cycle Time for CLK_MID
Clock to Setup (tCYC) 10.000 ns.
Pad to Pad Delay (tPD) 15.500 ns.
Clock Pad to Output Pad Delay (tCO) 19.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 10.0 7 7
AUTO_TS_P2P 0.0 19.0 73 73
AUTO_TS_P2F 0.0 1.8 1 1
AUTO_TS_F2P 0.0 17.2 13 13


Constraint: TS1000

Description: PERIOD:PERIOD_CLK_MID:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
AUDIO<0>.Q to AUDIO<1>.D 0.000 10.000 -10.000
AUDIO<0>.Q to AUDIO<2>.D 0.000 10.000 -10.000
AUDIO<0>.Q to AUDIO<3>.D 0.000 10.000 -10.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK_MID to A 0.000 19.000 -19.000
CLK_MID to B 0.000 19.000 -19.000
CLK_MID to C 0.000 19.000 -19.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK_MID to FCLKIO_0 0.000 1.800 -1.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
EN_DISP<0>.Q to A 0.000 17.200 -17.200
EN_DISP<0>.Q to B 0.000 17.200 -17.200
EN_DISP<0>.Q to C 0.000 17.200 -17.200



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK_MID 100.000 Limited by Cycle Time for CLK_MID

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock CLK_MID to Pad
Destination Pad Clock (edge) to Pad
A 19.000
B 19.000
C 19.000
D 19.000
E 19.000
F 19.000
G 18.000
AUDIO<0> 10.300
AUDIO<1> 10.300
AUDIO<2> 10.300
AUDIO<3> 10.300
EN_DISP<0> 10.300
EN_DISP<1> 10.300


Clock to Setup Times for Clocks

Clock to Setup for clock CLK_MID
Source Destination Delay
AUDIO<0>.Q AUDIO<1>.D 10.000
AUDIO<0>.Q AUDIO<2>.D 10.000
AUDIO<0>.Q AUDIO<3>.D 10.000
AUDIO<1>.Q AUDIO<2>.D 10.000
AUDIO<1>.Q AUDIO<3>.D 10.000
AUDIO<2>.Q AUDIO<3>.D 10.000
EN_DISP<0>.Q EN_DISP<1>.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
DIP<0> A 15.500
DIP<0> B 15.500
DIP<0> F 15.500
DIP<1> A 15.500
DIP<1> B 15.500
DIP<1> F 15.500
DIP<2> A 15.500
DIP<2> B 15.500
DIP<3> A 15.500
DIP<3> B 15.500
DIP<3> F 15.500
DIP<4> A 15.500
DIP<4> B 15.500
DIP<4> C 15.500
DIP<4> D 15.500
DIP<4> F 15.500
DIP<5> A 15.500
DIP<5> B 15.500
DIP<5> C 15.500
DIP<5> D 15.500
DIP<5> E 15.500
DIP<5> F 15.500
DIP<6> A 15.500
DIP<6> B 15.500
DIP<6> C 15.500
DIP<6> D 15.500
DIP<6> E 15.500
DIP<6> F 15.500
DIP<7> A 15.500
DIP<7> B 15.500
DIP<7> C 15.500
DIP<7> D 15.500
DIP<7> E 15.500
DIP<7> F 15.500
DIP<0> C 14.500
DIP<0> D 14.500
DIP<0> E 14.500
DIP<0> G 14.500
DIP<1> C 14.500
DIP<1> D 14.500
DIP<1> E 14.500
DIP<1> G 14.500
DIP<2> C 14.500
DIP<2> D 14.500
DIP<2> E 14.500
DIP<2> F 14.500
DIP<2> G 14.500
DIP<3> C 14.500
DIP<3> D 14.500
DIP<3> E 14.500
DIP<3> G 14.500
DIP<4> E 14.500
DIP<4> G 14.500
DIP<5> G 14.500
DIP<6> G 14.500
DIP<7> G 14.500
TASTER_D LED<3> 14.500
TASTER_L LED<1> 14.500
TASTER_R LED<2> 14.500
TASTER_U LED<0> 14.500



Number of paths analyzed: 94
Number of Timing errors: 94
Analysis Completed: Wed Apr 29 16:34:54 2009