cpldfit: version K.39 Xilinx Inc. Fitter Report Design Name: main Date: 4-29-2009, 4:34PM Device Used: XC9572XL-10-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 18 /72 ( 25%) 62 /360 ( 17%) 19 /216 ( 9%) 6 /72 ( 8%) 32 /34 ( 94%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 4/18 4/54 4/90 7/ 9 FB2 3/18 2/54 3/90 9/ 9* FB3 4/18 4/54 7/90 9/ 9* FB4 7/18 9/54 48/90 7/ 7* ----- ----- ----- ----- 18/72 19/216 62/360 32/34 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_MID' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 13 13 | I/O : 28 28 Output : 18 18 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 32 32 ** Power Data ** There are 18 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 18 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State LED<0> 1 1 FB1_2 1~ I/O O STD SLOW LED<1> 1 1 FB1_5 2~ I/O O STD SLOW LED<2> 1 1 FB1_6 3~ I/O O STD SLOW LED<3> 1 1 FB1_8 4~ I/O O STD SLOW DP 0 0 FB2_2 35~ I/O O STD SLOW EN_DISP<1> 2 2 FB2_5 36~ I/O O STD SLOW SET EN_DISP<0> 1 1 FB2_6 37~ I/O O STD SLOW RESET AUDIO<0> 1 1 FB3_11 18~ I/O O STD SLOW RESET AUDIO<1> 2 2 FB3_15 20~ I/O O STD SLOW RESET AUDIO<3> 2 4 FB3_16 24~ I/O O STD SLOW RESET AUDIO<2> 2 3 FB3_17 22~ I/O O STD SLOW RESET G 4 9 FB4_2 25~ I/O O STD SLOW D 8 9 FB4_5 26~ I/O O STD SLOW C 6 9 FB4_8 27~ I/O O STD SLOW F 8 9 FB4_11 28~ I/O O STD SLOW E 6 9 FB4_14 29~ I/O O STD SLOW B 8 9 FB4_15 33~ I/O O STD SLOW A 8 9 FB4_17 34~ I/O O STD SLOW ** 14 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK_MID FB1_14 7~ GCK/I/O GCK DIP<6> FB1_15 8~ I/O I DIP<5> FB1_17 9~ I/O I TASTER_RES FB2_8 38~ I/O I TASTER_R FB2_9 39~ GSR/I/O I TASTER_L FB2_11 40~ GTS/I/O I TASTER_D FB2_14 42~ GTS/I/O I TASTER_U FB2_15 43~ I/O I DIP<7> FB2_17 44~ I/O I DIP<4> FB3_2 11~ I/O I DIP<3> FB3_5 12~ I/O I DIP<2> FB3_8 13~ I/O I DIP<1> FB3_9 14~ I/O I DIP<0> FB3_14 19~ I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 4/50 Number of signals used by logic mapping into function block: 4 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) LED<0> 1 0 0 4 FB1_2 1~ I/O O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) LED<1> 1 0 0 4 FB1_5 2~ I/O O LED<2> 1 0 0 4 FB1_6 3~ I/O O (unused) 0 0 0 5 FB1_7 (b) LED<3> 1 0 0 4 FB1_8 4~ I/O O (unused) 0 0 0 5 FB1_9 5 GCK/I/O (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 6 GCK/I/O (unused) 0 0 0 5 FB1_12 (b) (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 7 GCK/I/O GCK (unused) 0 0 0 5 FB1_15 8 I/O I (unused) 0 0 0 5 FB1_16 (b) (unused) 0 0 0 5 FB1_17 9 I/O I (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: TASTER_D 3: TASTER_R 4: TASTER_U 2: TASTER_L Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LED<0> ...X.................................... 1 LED<1> .X...................................... 1 LED<2> ..X..................................... 1 LED<3> X....................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 2/52 Number of signals used by logic mapping into function block: 2 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) DP 0 0 0 5 FB2_2 35~ I/O O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) EN_DISP<1> 2 0 0 3 FB2_5 36~ I/O O EN_DISP<0> 1 0 0 4 FB2_6 37~ I/O O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 38 I/O I (unused) 0 0 0 5 FB2_9 39 GSR/I/O I (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 40 GTS/I/O I (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 42 GTS/I/O I (unused) 0 0 0 5 FB2_15 43 I/O I (unused) 0 0 0 5 FB2_16 (b) (unused) 0 0 0 5 FB2_17 44 I/O I (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: EN_DISP<0> 2: TASTER_RES Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DP ........................................ 0 EN_DISP<1> XX...................................... 2 EN_DISP<0> .X...................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 4/50 Number of signals used by logic mapping into function block: 4 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 11 I/O I (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 12 I/O I (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 13 I/O I (unused) 0 0 0 5 FB3_9 14 I/O I (unused) 0 0 0 5 FB3_10 (b) AUDIO<0> 1 0 0 4 FB3_11 18~ I/O O (unused) 0 0 0 5 FB3_12 (b) (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 19 I/O I AUDIO<1> 2 0 0 3 FB3_15 20~ I/O O AUDIO<3> 2 0 0 3 FB3_16 24~ I/O O AUDIO<2> 2 0 0 3 FB3_17 22~ I/O O (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: AUDIO<0> 3: AUDIO<2> 4: TASTER_RES 2: AUDIO<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs AUDIO<0> ...X.................................... 1 AUDIO<1> X..X.................................... 2 AUDIO<3> XXXX.................................... 4 AUDIO<2> XX.X.................................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 9/45 Number of signals used by logic mapping into function block: 9 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) G 4 0 0 1 FB4_2 25~ I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 \/2 3 FB4_4 (b) (b) D 8 3<- 0 0 FB4_5 26~ I/O O (unused) 0 0 /\1 4 FB4_6 (b) (b) (unused) 0 0 \/1 4 FB4_7 (b) (b) C 6 1<- 0 0 FB4_8 27~ I/O O (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 \/2 3 FB4_10 (b) (b) F 8 3<- 0 0 FB4_11 28~ I/O O (unused) 0 0 /\1 4 FB4_12 (b) (b) (unused) 0 0 \/1 4 FB4_13 (b) (b) E 6 1<- 0 0 FB4_14 29~ I/O O B 8 3<- 0 0 FB4_15 33~ I/O O (unused) 0 0 /\3 2 FB4_16 (b) (b) A 8 3<- 0 0 FB4_17 34~ I/O O (unused) 0 0 /\3 2 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: DIP<0> 4: DIP<3> 7: DIP<6> 2: DIP<1> 5: DIP<4> 8: DIP<7> 3: DIP<2> 6: DIP<5> 9: EN_DISP<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs G XXXXXXXXX............................... 9 D XXXXXXXXX............................... 9 C XXXXXXXXX............................... 9 F XXXXXXXXX............................... 9 E XXXXXXXXX............................... 9 B XXXXXXXXX............................... 9 A XXXXXXXXX............................... 9 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** A <= ((EXP13_.EXP) OR (EN_DISP(0) AND DIP(4) AND DIP(5) AND NOT DIP(6)) OR (EN_DISP(0) AND DIP(5) AND NOT DIP(6) AND NOT DIP(7)) OR (NOT EN_DISP(0) AND DIP(0) AND DIP(1) AND NOT DIP(2)) OR (NOT EN_DISP(0) AND DIP(1) AND NOT DIP(2) AND NOT DIP(3)) OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(1) AND DIP(2) AND DIP(3))); FTCPE_AUDIO0: FTCPE port map (AUDIO(0),'1',CLK_MID,NOT TASTER_RES,'0'); FTCPE_AUDIO1: FTCPE port map (AUDIO(1),AUDIO(0),CLK_MID,NOT TASTER_RES,'0'); FTCPE_AUDIO2: FTCPE port map (AUDIO(2),AUDIO_T(2),CLK_MID,NOT TASTER_RES,'0'); AUDIO_T(2) <= (AUDIO(0) AND AUDIO(1)); FTCPE_AUDIO3: FTCPE port map (AUDIO(3),AUDIO_T(3),CLK_MID,NOT TASTER_RES,'0'); AUDIO_T(3) <= (AUDIO(0) AND AUDIO(1) AND AUDIO(2)); B <= ((EXP12_.EXP) OR (EN_DISP(0) AND DIP(4) AND NOT DIP(6) AND NOT DIP(7)) OR (EN_DISP(0) AND NOT DIP(4) AND NOT DIP(5) AND NOT DIP(7)) OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(1) AND NOT DIP(2)) OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(2) AND NOT DIP(3)) OR (NOT EN_DISP(0) AND NOT DIP(0) AND NOT DIP(1) AND NOT DIP(3))); C <= ((EXP8_.EXP) OR (EN_DISP(0) AND DIP(4) AND NOT DIP(6) AND NOT DIP(7)) OR (EN_DISP(0) AND NOT DIP(5) AND NOT DIP(6) AND NOT DIP(7)) OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(2) AND NOT DIP(3)) OR (NOT EN_DISP(0) AND NOT DIP(1) AND NOT DIP(2) AND NOT DIP(3)) OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(1) AND DIP(2) AND DIP(3))); D <= ((EXP6_.EXP) OR (EXP7_.EXP) OR (EN_DISP(0) AND NOT DIP(4) AND NOT DIP(5) AND NOT DIP(6)) OR (NOT EN_DISP(0) AND NOT DIP(0) AND NOT DIP(1) AND NOT DIP(2)) OR (NOT EN_DISP(0) AND DIP(0) AND DIP(1) AND NOT DIP(2) AND DIP(3)) OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(1) AND DIP(2) AND NOT DIP(3)) OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(1) AND DIP(2) AND DIP(3))); DP <= '0'; E <= ((EXP11_.EXP) OR (EN_DISP(0) AND NOT DIP(4) AND DIP(7)) OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(3)) OR (EN_DISP(0) AND NOT DIP(4) AND DIP(5) AND DIP(6)) OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(1) AND DIP(2)) OR (NOT EN_DISP(0) AND DIP(1) AND NOT DIP(2) AND DIP(3))); FTCPE_EN_DISP0: FTCPE port map (EN_DISP(0),'1',CLK_MID,NOT TASTER_RES,'0'); FDCPE_EN_DISP1: FDCPE port map (EN_DISP(1),EN_DISP(0),CLK_MID,'0',NOT TASTER_RES); F <= ((EXP9_.EXP) OR (EXP10_.EXP) OR (EN_DISP(0) AND DIP(5) AND NOT DIP(6) AND NOT DIP(7)) OR (EN_DISP(0) AND NOT DIP(5) AND DIP(6) AND DIP(7)) OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(2) AND DIP(3)) OR (NOT EN_DISP(0) AND DIP(1) AND NOT DIP(2) AND NOT DIP(3)) OR (NOT EN_DISP(0) AND NOT DIP(1) AND DIP(2) AND DIP(3))); G <= ((EN_DISP(0) AND DIP(5) AND DIP(6) AND DIP(7)) OR (NOT EN_DISP(0) AND DIP(1) AND DIP(2) AND DIP(3)) OR (EN_DISP(0) AND NOT DIP(4) AND NOT DIP(5) AND NOT DIP(6) AND DIP(7)) OR (NOT EN_DISP(0) AND NOT DIP(0) AND NOT DIP(1) AND NOT DIP(2) AND DIP(3))); LED(0) <= TASTER_U; LED(1) <= TASTER_L; LED(2) <= TASTER_R; LED(3) <= TASTER_D; Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-10-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572XL-10-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 LED<0> 23 GND 2 LED<1> 24 AUDIO<3> 3 LED<2> 25 G 4 LED<3> 26 D 5 TIE 27 C 6 TIE 28 F 7 CLK_MID 29 E 8 DIP<6> 30 TDO 9 DIP<5> 31 GND 10 GND 32 VCC 11 DIP<4> 33 B 12 DIP<3> 34 A 13 DIP<2> 35 DP 14 DIP<1> 36 EN_DISP<1> 15 TDI 37 EN_DISP<0> 16 TMS 38 TASTER_RES 17 TCK 39 TASTER_R 18 AUDIO<0> 40 TASTER_L 19 DIP<0> 41 VCC 20 AUDIO<1> 42 TASTER_D 21 VCC 43 TASTER_U 22 AUDIO<2> 44 DIP<7> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : SLOW Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : FLOAT Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25