Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State |
---|---|---|---|---|---|---|---|---|---|---|
A | 4 | 4 | FB4 | MC17 | STD | SLOW | 34 | I/O | O | |
B | 5 | 4 | FB4 | MC15 | STD | SLOW | 33 | I/O | O | |
C | 3 | 4 | FB4 | MC8 | STD | SLOW | 27 | I/O | O | |
D | 4 | 4 | FB4 | MC5 | STD | SLOW | 26 | I/O | O | |
E | 3 | 4 | FB4 | MC14 | STD | SLOW | 29 | I/O | O | |
EN_DISP<0> | 1 | 1 | FB2 | MC6 | STD | FAST | 37 | I/O | O | RESET |
EN_DISP<1> | 2 | 2 | FB2 | MC5 | STD | FAST | 36 | I/O | O | SET |
F | 4 | 4 | FB4 | MC11 | STD | SLOW | 28 | I/O | O | |
G | 2 | 4 | FB4 | MC2 | STD | SLOW | 25 | I/O | O | |
LED<0> | 2 | 4 | FB1 | MC2 | STD | SLOW | 1 | I/O | O | SET |
LED<1> | 2 | 5 | FB1 | MC5 | STD | SLOW | 2 | I/O | O | SET |
$OpTx$FX_DC$11 | 1 | 4 | FB4 | MC1 | STD | (b) | (b) | |||
$OpTx$FX_DC$12 | 1 | 4 | FB1 | MC6 | STD | 3 | I/O | (b) | ||
$OpTx$FX_DC$3 | 4 | 6 | FB2 | MC18 | STD | (b) | (b) | |||
$OpTx$FX_DC$6 | 1 | 4 | FB2 | MC12 | STD | (b) | (b) | |||
$OpTx$FX_DC$7 | 1 | 4 | FB2 | MC11 | STD | 40 | I/O/GTS2 | (b) | ||
$OpTx$FX_DC$9 | 1 | 3 | FB1 | MC4 | STD | (b) | (b) | |||
XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D | 2 | 2 | FB3 | MC16 | STD | 24 | I/O | (b) | ||
XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D | 2 | 2 | FB3 | MC15 | STD | 20 | I/O | (b) | ||
XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2 | 3 | 6 | FB4 | MC7 | STD | (b) | (b) | |||
XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2 | 3 | 3 | FB3 | MC17 | STD | 22 | I/O | (b) | ||
XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D | 2 | 2 | FB2 | MC13 | STD | (b) | (b) | |||
XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2 | 3 | 3 | FB4 | MC6 | STD | (b) | (b) | |||
XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2 | 3 | 4 | FB4 | MC4 | STD | (b) | (b) | |||
XLXN_163 | 1 | 1 | FB1 | MC3 | STD | (b) | (b) | RESET | ||
XLXN_204 | 1 | 1 | FB2 | MC10 | STD | (b) | (b) | RESET | ||
XLXN_307/XLXN_307_D2 | 4 | 6 | FB3 | MC18 | STD | (b) | (b) | |||
accu_in<0> | 3 | 4 | FB4 | MC3 | STD | (b) | (b) | RESET | ||
accu_in<1> | 4 | 5 | FB4 | MC13 | STD | (b) | (b) | RESET | ||
accu_in<2> | 4 | 6 | FB4 | MC12 | STD | (b) | (b) | RESET | ||
accu_in<3> | 4 | 5 | FB2 | MC17 | STD | 44 | I/O | (b) | RESET | |
accu_in<4> | 3 | 5 | FB1 | MC11 | STD | 6 | I/O/GCK2 | GCK | RESET | |
accu_in<5> | 3 | 5 | FB1 | MC10 | STD | (b) | (b) | RESET | ||
accu_in<5>/accu_in<5>_CE | 1 | 3 | FB1 | MC1 | STD | (b) | (b) | |||
accu_in<6> | 3 | 5 | FB1 | MC9 | STD | 5 | I/O/GCK1 | (b) | RESET | |
accu_in<7> | 3 | 5 | FB1 | MC8 | STD | 4 | I/O | (b) | RESET | |
accu_out<0> | 3 | 4 | FB1 | MC7 | STD | (b) | (b) | RESET | ||
accu_out<1> | 5 | 7 | FB4 | MC18 | STD | (b) | (b) | RESET | ||
accu_out<2> | 4 | 5 | FB4 | MC10 | STD | (b) | (b) | RESET | ||
accu_out<3> | 4 | 5 | FB4 | MC9 | STD | (b) | (b) | RESET | ||
accu_out<4> | 5 | 7 | FB4 | MC16 | STD | (b) | (b) | RESET | ||
accu_out<5> | 4 | 5 | FB1 | MC15 | STD | 8 | I/O | (b) | RESET | |
accu_out<6> | 4 | 5 | FB1 | MC14 | STD | 7 | I/O/GCK3 | (b) | RESET | |
accu_out<7> | 6 | 7 | FB1 | MC17 | STD | 9 | I/O | (b) | RESET | |
cnt<0> | 4 | 5 | FB1 | MC13 | STD | (b) | (b) | RESET | ||
cnt<1> | 5 | 8 | FB1 | MC16 | STD | (b) | (b) | RESET | ||
cnt<2> | 4 | 5 | FB1 | MC12 | STD | (b) | (b) | RESET | ||
cnt<3> | 3 | 4 | FB2 | MC14 | STD | 42 | I/O/GTS1 | (b) | RESET | |
d2/d2_D2 | 4 | 6 | FB2 | MC16 | STD | (b) | (b) | |||
d3/d3_D2 | 4 | 6 | FB2 | MC15 | STD | 43 | I/O | I |